Wafer inspection systems help a semiconductor manufacturer increase and maintain integrated circuit (IC) chip yields by detecting defects that occur during the manufacturing process. One purpose of inspection systems is to monitor whether a manufacturing process meets specifications. The inspection system indicates the problem and/or the source of the problem if the manufacturing process is outside the scope of established norms, which the semiconductor manufacturer can then address.
Evolution of the semiconductor manufacturing industry is placing ever greater demands on yield management and, in particular, on metrology and inspection systems. Critical dimensions are shrinking while wafer size is increasing. Economics is driving the industry to decrease the time for achieving high-yield, high-value production. Thus, minimizing the total time from detecting a yield problem to fixing it determines the return-on-investment for the semiconductor manufacturer.
Defect detection on semiconductor wafers can be complicated and time-consuming. Semiconductor manufacturers need improved techniques to detect defects in a faster and more reliable manner.
In a first technique, design rule based scripting language was used to define inspection regions that satisfy the rules, group such regions into sensitivity regions, analyze noise characteristics of each such region during inspection recipe setup, and tune sensitivity thresholds per sensitivity region. Not all critical regions are known a priori by a semiconductor manufacturer, which is a drawback of the first technique. With each design node and process change, the types of critical regions can vary. It is only through inspection and review that such new regions are discovered. It also is not easy to infer which rules best describe these newly discovered regions. Design rule based scripting language relies on general rules (e.g., described using a scripting language such as Standard Verification Rule Format (SVRF)) to generate inspection regions. Regarding noise estimation, design rule based scripting language may measure noise of each region, but this noise covers a large variety of contexts and is equivalent to mixing populations which have distinct and different noise characteristics.
In a second technique, design clips of patterns of interest (POI) or “hot spots” are provided. A design database is searched (e.g., using a pattern search tool) for all locations of these patterns in the die and then the regions are inspected using a sensitive threshold. The second technique suffers from the same drawbacks as the first technique. Not all POI are discovered easily, even with experiments using process window qualification (PWQ) wafers. The POI known to the user may only cover part of the total set of “weak” patterns. The total coverage of hot spot care areas is generally low (e.g., in the 1% range), even when there are millions of them. In this example, a care area (CA) group can include a set of rectangles (or polygons) on the surface of a die that can be combined. If the number hot spot care area groups are increased to several thousand to have a better coverage, every CA group would need to be tuned independently, which is not practical. One particular risk of hot spot care areas is that there are areas which are not covered by them, which might result in missing defects and excursions because the sensitivity in the areas not covered by hot spots is too insensitive. Moreover, the current methods make no use of the wafer image information for determining how such critical regions should be grouped together for purposes of finding outliers (e.g., potential defects). Without performing some grouping of such regions, there may not be sufficient pixels in order to robustly determine which pixels are potential defects.
In a third technique, a “hot” inspection of the wafer is run. A hot inspection is one where the detection threshold (e.g., the minimum difference in die-to-die gray level) to determine whether a pixel is defective or not is set to a low value. Hence, such a detection recipe would find a large number of “defects.” One can the tune the threshold to catch only the real defects and filter out false detections such as noise or nuisance defects. Resulting defect locations are grouped using design-based grouping (DBG). Groups that contain defects of interest versus nuisance defects are determined, then all locations where such patterns of interest exist on the die are found (e.g., using a pattern search tool) and inspection sensitivity regions are created at these locations for subsequent inspection recipes. This third technique relies on a uniformly hot inspection to discover weak areas. Unfortunately, the resulting number of DBG bins can be excessive and sampling each bin sufficiently may be too cumbersome in terms of review time on a scanning electron microscope (SEM) review tool. Discarding DBG bins containing too few defects from review may result in missing a critical defect type. Also, such a review sampling strategy often ends up reviewing an excessive number of nuisance defects, such as those caused by color changes across dies due to film thickness variations, edge roughness, or other features. This large number of nuisance defects can result in the sample set missing critical defects present in those bins. DBG does not combine structures which have the same noise values, which generates a large number of groups (bins) that cannot be handled by a user to separately tune them. The noise floor calculation is not done for all the structures within one die and group, which can make it unstable due to limited statistics. It also does not consider the noisiness of a certain structure.
Therefore, what is needed is improved defect sensitivity during wafer inspection using design data in combination with wafer image data.